ADSP-21065LKCA-264 データシートの表示（PDF） - Analog Devices
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ADSP-21065LKCA-264 Datasheet PDF : 44 Pages
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ADSP-21065L
Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con-
nected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera-
tion. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
Parameter
Clock Input
Timing Requirements:
tCK
tCKL
tCKH
tCKRF
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
66 MHz
Min
Max
30.00
100
7.0
5.0
3.0
60 MHz
Min
Max
33.33
100
7.0
5.0
3.0
Unit
ns
ns
ns
ns
CLKIN
t CK
t CKH
t CKL
Figure 7. Clock Input
Parameter
Min
Max
Unit
Reset
Timing Requirements:
tWRST
tSRST
RESET Pulsewidth Low1
RESET Setup Before CLKIN High2
2 tCK
ns
23.5 + 24 DT tCK
ns
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
CLKIN
RESET
t WRST
t SRST
Figure 8. Reset
Parameter
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup Before CLKIN High or Low1
tHIR
IRQ2-0 Hold Before CLKIN High or Low1
tIPW
IRQ2-0 Pulsewidth2
NOTES
1Only required for IRQx recognition in the following cycle.
2Applies only if tSIR and tHIR requirements are not met.
Min
Max
Unit
11.0 + 12 DT
ns
0.0 + 12 DT ns
2.0 + tCK/2
ns
–14–
REV. C
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