HFA3861 データシートの表示（PDF） - Intersil

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HFA3861

Direct Sequence Spread Spectrum Baseband Processor

Intersil 

HFA3861

7

8

THY 1, 2

Eb/N0

9

10

11

12

1.E+00

1.E-01

BER 2.0

BER 1.0

1.E-02

1.E-03

1.E-04

1.E-05

1.E-06

1.E-07

1.E-08

FIGURE 14. BER vs Eb/N0 PERFORMANCE FOR PSK MODES

56 7

1.E+00

1.E-01

1.E-02

1.E-03

1.E-04 THY 11

1.E-05

THY 5.5

1.E-06

1.E-07

1.E-08

1.E-09

Eb/N0

8 9 10 11 12 13 14

BER 11

BER 5.5

FIGURE 15. BER vs Eb/N0 PERFORMANCE FOR CCK MODES

Clock Offset Tracking Performance

The PRISM baseband processor is designed to accept data

clock offsets of up to ±25ppm for each end of the link (TX

and RX). This effects both the acquisition and the tracking

performance of the demodulator. The budget for clock offset

error is 0.75dB at ±50ppm. No appreciable degradation was

seen for operation in AWGN at ±50ppm.

Carrier Offset Frequency Performance

The correlators used for acquisition for all modes and for

demodulation in the 1 and 2Mbps modes are time invariant

matched filter correlators otherwise known as parallel

correlators. They use two samples per chip and are tapped

at every other shift register stage. Their performance with

carrier frequency offsets is determined by the phase roll rate

due to the offset. For an offset of +50ppm (combined for both

TX and RX) will cause the carrier to phase roll 22.5 degrees

over the length of the correlator. This causes a loss of

0.22dB in correlation magnitude which translates directly to

Eb/N0 performance loss. In the PRISM chip design, the

correlator is not included in the carrier phase locked loop

correction during acquisition.

20

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