![](/html/UTMC/91733/page8.png)
EN
R IN+
RIN-
VDD
2K
10pf
2K
ENT Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit
EN when EN = VDD
EN when EN = VSS
Output when
VID = -100mV
Output when
VID = +100mV
1.5V
1.5V
PM 1.5V
O tPLZ
DEVEL tPHZ
1.5V
0.5V
0.5V
tPZL
tPZH
VD D
0V
VDD
0V
50%
50%
VOZ
VOL
VOH
IN
VOZ
Figure 7. Receiver Three-State Delay Waveform
8