XRT83L38 データシートの表示（PDF） - Exar Corporation
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XRT83L38 Datasheet PDF : 91 Pages
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XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
RDY_DTACK
EQC4
µPTS1
µPTS2
TQFP
PIN #
BGA
LEAD
#
TYPE
DESCRIPTION
194 A6 O Ready Output (Data Transfer Acknowledge Output) - Host mode
Intel bus timing: RDY is asserted “High” to indicate the device has completed
a read or write operation.
Motorola bus timing: DTACK is asserted “Low” to indicate the device has
completed a read or write cycle.
194 A6
I Equalizer Control Input pin 4 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. See “Receive Equalizer Control and Transmit Line
Build-Out Settings” on page 30.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
133 J16
128 L15
Microprocessor Type Select Input Pins - Host Mode:
I Microprocessor Type Select Input Bit 1
Microprocessor Type Select Input Bit 2
µPTS2
0
0
1
1
µPTS1
0
1
0
1
µP Type
68HC11, 8051, 80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Motorola 860 (sync.)
RCLKE
TCLKE
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
133 J16
128 L15
Receive Clock Edge - Hardware mode
See “Receive Clock Edge - Hardware mode” on page 7.
Transmit Clock Edge - Hardware mode
See “Transmit Clock Edge - Hardware mode” on page 7.
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
Microprocessor Read/Write Data Bus Pins - Host mode
67
T7 I/O Data Bus[7]
68
U7
Data Bus[6]
69
V7
Data Bus[5]
70
V8
Data Bus[4]
71
V9
Data Bus[3]
72
U8
Data Bus[2]
73
U9
Data Bus[1]
74
R7
Data Bus[0]
67
T7
68
U7
69
V7
70
V8
71
V9
72
U8
73
U9
74
R7
Loop-back Control Pins, Bits [1:0] Channel_[7:4] - Hardware Mode
Pins 67-74 and 173-180 control which Loop-Back mode is selected per chan-
nel. See “Loop-back Control Pins, Bits [1:0] Channel_[7:0]” on page 17.
NOTE: Internally pulled “Low” with a 50kΩ resistor for all channels.
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