MTL007 データシートの表示（PDF） - Myson Century Inc
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MTL007 Datasheet PDF : 65 Pages
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MTL007
PIN DESCRIPTION
ADC Input Interface (RGB or YUV or TMDS Input Data)
Name
IPCLK
VSYNC
HSYNC/CS
RIN[7:0]/YIN[7:0]
(RIN[5:0])
GIN[7:0]/UVIN[7:0]
(GIN[5:0])
Type
I
I
I
I
I
BIN[7:0]
(BIN[5:0])
I
RAWHS
I
TDIE
I
CLAMP
O
Pin No.
92
94
93
91-84
(89-84)
82-75
(78-75, 91, 90)
74-67
(68, 67, 82-79)
62
66
60
Description
Input pixel clock
Input Vertical sync
Input Horizontal or Composite sync
Red or Y channel or TMDS input data
(Red channel for 6-bit input)
Green or UV channel or TMDS input data
(Green channel for 6-bit input)
Blue or TMDS input data, or Control bit for YUV video input
Bit 4: VPHREF, Video input Horizontal reference signal
Bit 3: VPVS, Video input VSYNC signal
Bit 2: VPODD, Video input ODD/EVEN field signal
Bit 1: VPHS, Video input HSYNC signal
Bit 0: VPCLK, Video input clock signal
(Blue channel for 6-bit input)
Input source HSYNC for measurement
TMDS digital input enable
Clamp pulse output for ADC
Display Output Interface
Name
Type
DDCLK1
DVSYNC
O
OE
O
DHSYNC
O
DDCLK2
O
R1OUT[0:7]
O
G1OUT[0:7]
O
B1OUT[0:7]
O
R2OUT[0:7]
O
G2OUT[0:7]
O
B2OUT[0:7]
O
Pin No.
Description
1
Display output clock
37
Display Vertical sync output
39
Display output enable
35
Display Horizontal sync output
38
Display output clock
33-30, 28, 26-25, 23 Red output even data , bit[7:2] for 6-rlogin rbit panel
22, 20-15, 13 Green output even data , bit[7:2] for 6-bit panel
11-9, 7, 5-3, 2 Blue output even data , bit[7:2] for 6-bit panel
128-127, 125-124,
122-119
Red output odd data
, bit[7:2] for 6-bit panel
118,117, 115, 113-
111, 109,107
Green output odd data , bit[7:2] for 6-bit panel
106-101, 99-98 Blue output odd data , bit[7:2] for 6-bit panel
Host Interface
Name
RST#
SCL
Type
I
I
Pin No.
44
48
Description
System reset input, active low.
Serial bus clock
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