ISL6112 データシートの表示（PDF） - Renesas Electronics

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ISL6112

Dual Slot PCI-Express Hot Plug Controller

Renesas Electronics 

ISL6112

(1)

AUXEN

(2)

VAUX

(3)

3VAUX_UV

(1)

ON

(4)

MAIN

(3)

12VOUT_UV

3VOUT_UV

(3)

(1)

FORCE_ON

(5)

FORCE_EN

VSTBY

PWRGD

(1) EXTERNAL PIN

(2) CNTRL REGISTER BIT D[0]

(3) INTERNAL FLAG

(4) CNTRL REGISTER BIT D[1]

(5) CNTRL REGISTER BIT D[2]

FIGURE 30. PWRGD LOGIC DIAGRAM

Fault Reporting and Interrupt Generation

SMI-ONLY CONTROL APPLICATIONS

For applications in which the ISL6112 is controlled only by SMI,

ON and AUXEN are connected to GND, and the FORCE_ON pins

are either shorted or are connected to VSTBY as shown in

Figure 27. In these cases, the ISL6112 FAULT outputs and

STATUS Register Bit D[7] (FAULT) are not activated, because fault

status is determined by polling STATUS Register Bits D[4], D[2],

D[0] and CS (Common Status) Register Bits D[2:1]. Individual

fault bits in the STATUS and CS registers are asserted after POR,

when:

• Either or both CNTRL Register Bits D[1:0] are asserted, AND

• 12VIN, 3VIN, or VSTBY input voltage is lower than its respective

ULVO threshold, OR

• The fast OC circuit isolation protection has tripped, OR

• The slow OC circuit isolation protection has tripped AND its

filter time-out has expired, OR

• The slow OC circuit isolation protection has tripped AND Slot

die temperature > +140°C, OR

• The ISL6112 global die temperature > +160°C

Once asserted, to clear any one or all STATUS Register Bits D[4],

D[2], D[0] or CS Register Bits D[2], D[1], a software subroutine

can perform an “echo reset” in which a Logical “1” is written

back to those register bit locations that have indicated a fault.

This method of “echo reset” allows data to be retained in the

STATUS and/or CS registers until such time as the system is

prepared to operate on that data.

The ISL6112 can operate in interrupt mode or polled mode. For

interrupt-mode operation, the open-drain, active-LOW INT output

signal is activated after POR if the INTMSK bit (CS Register Bit

D[3]) has been reset to Logical “0”. Once activated, the INT

output is asserted by any one of the fault conditions previously

listed. It is deasserted when one or all STATUS Register Bits D[4],

D[2], D[0] or CS Register Bits D[2], D[1] are reset upon the

execution of an SMBus “echo reset” WRITE_BYTE cycle. For

polled-mode operation, the INTMSK bit should be set to Logical

“1,” thereby inhibiting INT output pin operation.

For SMI control applications in which the FORCE_ON inputs are

needed for diagnostic purposes, the FORCE_ON inputs must be

enabled; that is, CNTRL Register Bit D[2] should read Logical “0.”

Once FORCE_ON inputs are asserted, all output voltages are

present with all circuit protection features disabled, including

over-temperature protection on VAUX outputs. To inhibit

FORCE_ON operation, a Logical “1” is written to the CNTRL

Register Bit D[2] locations.

HPI-ONLY CONTROL APPLICATIONS

For applications in which the ISL6112 is controlled only by HPI,

SMBus signals SCL, SDA, and INT are connected to VSTBY as

shown in Figure 27. In this configuration, the ISL6112 FAULT

outputs are activated after POR and become asserted when:

Either or both external ON and AUXEN input signals are asserted,

AND

• 12VIN, 3VIN, or VSTBY input voltage is lower than its respective

ULVO threshold, OR

• The fast OC circuit isolation protection has tripped, OR

• The slow OC circuit isolation protection has tripped AND its

filter time-out has expired, OR

• The slow OC circuit isolation protection has tripped AND slot

die temperature > +140°C, OR

• The ISL6112 global die temperature > +160°C.

To clear FAULT outputs, once asserted, either or both ON and

AUXEN input signals must be deasserted. (See FAULT pin in “Pin

Descriptions” table on page 4 for additional information.) If the

FORCE_ON inputs are used for diagnostic purposes, both the

FAULT and PWRGD outputs are deasserted after the FORCE_ON

inputs are asserted.

Serial Port Operation

The ISL6112 uses standard SMBus Write_Byte and Read_Byte

operations for communication with its host. The SMBus

Write_Byte operation involves sending the device’s target

address, with the R/W bit (LSB) set to the low (write) state,

followed by a command byte and a data byte. The SMBus

Read_Byte operation is similar, but it is a composite write and

read operation. The host first sends the device’s target address,

followed by the command byte, as in a write operation. A new

FN6456 Rev 1.00

August 25, 2011

Page 18 of 30

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