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tRR
MR
CLK
Q (P2)
Q (P4)
Q (P6)
Phase_Out (P4)
Phase_Out (P6)
MC100EL38
Figure 3. Timing Diagram
Q
Driver
Device
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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