IDT7188L55DB(1996) データシートの表示（PDF） - Integrated Device Technology
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IDT7188L55DB Datasheet PDF : 7 Pages
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IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
7188S25
7188L25
7188S35/45 7188S55/70 7188S85
7188L35/45 7188L55/70 7188L85
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
Write Cycle Time
20 — 30/40 — 50/60 — 75 — ns
tCW
Chip Select to End-of-Write
20 — 25/35 — 50/60 — 75 — ns
tAW
Address Valid to End-of-Write
20 — 25/35 — 50/60 — 75 — ns
tAS
Address Set-up Time
0 — 0 — 0 — 0 — ns
tWP
Write Pulse Width
20 — 25/35 — 50/60 — 75 — ns
tWR
Write Recovery Time
0 — 0 — 0 — 0 — ns
tDW
Data Valid to End-of-Write
13 — 15/20 — 25/30 — 35 — ns
tDH
tWZ(1)
tOW(1)
Data Hold Time
Write Enable to Output in High-Z
Output Active from End-of-Write
0 — 0 — 0 — 0 — ns
—
7 — 10/15 — 25/30 — 40 ns
5 — 5 — 5 — 5 — ns
NOTES:
1. This parameter is guaranteed by device characterization.
2989 tbl 12
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2 ,3)
tWC
ADDRESS
tAW
CS1, CS2
tAS
tWP (7)
tWR
WE
DATAOUT
tWZ (6)
(4)
tOW (6)
(4)
tDW
tDH
DATAIN
DATA VALID
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
2989 drw 08
6.3
6
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