A2927SEB データシートの表示（PDF） - Allegro MicroSystems

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A2927SEB

DUAL FULL-BRIDGE PWM MOTOR DRIVER

Allegro MicroSystems 

2927

DUAL FULL-BRIDGE

PWM MOTOR DRIVER

CURRENT-CONTROL

TRUTH TABLE

I0

I1

Output Current

L

L

VREF/10 RS = ITRIP

H

L

VREF/15 RS = 2/3 ITRIP

L

H

VREF /30 RS = 1/3 ITRIP

H

H

0

Loads with high distributed capacitances may result in

high turn-ON current peaks. This peak (appearing across

RS) will attempt to trip the comparator, resulting in errone-

ous current control or high-frequency oscillations. An

external RCCC low-pass filter may be needed to delay the

action of the comparator.

LOGIC CONTROL OF OUTPUT CURRENT:

Two logic level inputs (I0 and I1) allow digital selection

of the motor winding current at 100%, 67%, 33%, or 0% of

the maximum level per the table. The 0% output current

condition turns OFF all drivers in the bridge and can be

used as an output enable function. These logic level

inputs greatly enhance the implementation of µP-con-

trolled drive formats.

During half-step operations, the I0 and I1 inputs allow

the µP to control the motor at a constant torque between

all positions in an eight-step sequence. This is accom-

plished by digitally selecting 100% drive current when only

one phase is ON and 67% drive current when two phases

are ON.

The logic control inputs can also be used to select a

reduced current level (and reduced power dissipation) for

‘hold’ conditions and/or increased current (and available

torque) for start-up conditions.

GENERAL :

Both bridges have internal flyback diodes (connected

from the outputs to VBB) for protection against inductive

transients. External ground-clamp diodes (connected

from the outputs to ground) are required; Schottky

ground-clamp diodes are recommended to minimize on-

chip power dissipation.

To avoid excessive voltage spikes on the LOAD

SUPPLY terminal (VBB), a large-value capacitor (≥47 µF)

should be connected from VBB to ground as close as

possible to the device. Under no circumstances should

the voltage at LOAD SUPPLY exceed 50 V. A low-value

(0.1 µF) ceramic capacitor at this terminal may be used

for high-frequency noise suppression.

The PHASE input to each bridge determines the

direction motor winding current flows. An internally

generated deadtime (approximately 3 µs) prevents

crossover currents that can occur when switching the

PHASE input.

All four drivers in the bridge output can be turned OFF

(VEN ≥ 2.4 V or I0 = I1 ≥ 2.4 V), resulting in a fast current

decay through the internal flyback and external ground-

clamp diodes. The fast current decay is desirable in half-

step and high-speed applications. All logic inputs float

high; the ENABLE input must be tied low if it is not used.

Varying the reference voltage (VREF) provides continu-

ous control of the peak load current for micro-stepping

applications, within the specified limits for VREF.

Thermal protection circuitry turns OFF all drivers

when the junction temperature reaches approximately

+170°C. It is only intended to protect the device from

failures due to excessive junction temperature and should

not imply that output short circuits are permitted. The

output drivers are reenabled when the junction tempera-

ture cools to approximately +160°C.

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