V826516B04S データシートの表示（PDF） - Mosel Vitelic Corporation
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V826516B04S Datasheet PDF : 14 Pages
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MOSEL VITELIC
V826516B04S
DDR SDRAM IDD SPEC TABLE
Symbol
B1(DDR266@CL=2)
Typical
Worst
IDD0
630
690
IDD1
720
810
IDD2P
330
350
IDD2F
430
470
IDD2Q
390
410
IDD3P
370
390
IDD3N
450
490
IDD4R
950
1070
IDD4W
990
1130
IDD5
990
1090
IDD6 Normal
16
16
Low power
8
8
IDD7A
1610
1830
B0(DDR266@CL=2.5) A1(DDR200@CL=2)
Typical
Worst Typical Worst
630
690
550
590
720
810
650
730
330
350
270
290
430
470
370
390
390
410
330
350
370
390
310
330
450
490
370
410
950
1070
790
930
990
1130
830
990
990
1090
910
990
16
16
16
16
8
8
8
8
1610
1830
1310
1510
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
16
8
mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826516B04S Rev. 1.3 March 2002
9
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