TC58256AFTI データシートの表示（PDF） - Toshiba

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TC58256AFTI

256-MBIT (32M X 8 BITS) CMOS NAND E2PROM

Toshiba 

Read Cycle (2) Timing Diagram

CLE

CE

tCLS

tCS

tCLH

tCH

TC58256AFTI

WE

tALH

tALS

tALH

ALE

RE

tDS tDH

tDS tDH

tR

tWB

I/O1

01H

to I/O8

RY/BY

A0 toA7 A9 toA16 A17toA24

Column address

N*

* Read Operation using 01H Command N: 0 to 255

tAR2

tRR tRC

tREA

DOUT

DOUT

DOUT

256 + M 256 + M + 1 527

: VIH or VIL

Read Cycle (3) Timing Diagram

CLE

CE

tCLS

tCS

tCLH

tCH

WE

tALH

tALS

tALH

ALE

RE

tDS tDH

tDS tDH

tR

tWB

I/O1

50H

to I/O8

RY/BY

A0 toA7 A9 toA16 A17toA24

Column address

N*

* Read Operation using 50H Command N: 0 to 15

tAR2

tRR tRC

tREA

DOUT

DOUT

DOUT

512 + M 512 + M + 1 527

: VIH or VIL

2001-05-30 10/33

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