M48T02 データシートの表示（PDF） - STMicroelectronics
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M48T02 Datasheet PDF : 14 Pages
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M48T02, M48T12
Table 9. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
tAVAV
tAVWL
tAVEL
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
tWLQZ
tAVWH
tAVEH
tWHQX
Write Cycle Time
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
M48T02 / 12
-120
-150
-200
Unit
Min Max Min Max Min Max
120
150
200
ns
0
0
0
ns
0
0
0
ns
75
90
120
ns
75
90
120
ns
10
10
10
ns
10
10
10
ns
35
40
60
ns
35
40
60
ns
5
5
5
ns
5
5
5
ns
40
50
60
ns
90
120
140
ns
90
120
140
ns
10
10
10
ns
READ MODE
The M48T02,12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within tAVQV (Address Access Time) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
Time (tELQV) or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the AddressInputs
are changed while E and G remain active, output
data will remain valid for tAXQX (Output Data Hold
Time) but will go indeterminate until the next Ad-
dress Access.
WRITE MODE
The M48T02,12 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for minimum of
tEHAX from Chip Enable or tWHAX from Write Enable
prior to the initiation of another read or write cycle.
Data-in must be valid tDVWH prior to the end of write
and remain valid for tWHDX afterward. G should be
kept high during write cycles to avoid bus conten-
tion; although, if the output bus has been activated
by a low on E and G, a low on W will disable the
outputs tWLQZ after W falls.
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