M40Z300MH データシートの表示（PDF） - STMicroelectronics
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M40Z300MH Datasheet PDF : 25 Pages
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Operation
M40Z300, M40Z300W
2.1
Two to four decode
The M40Z300/W includes a 2 input (A, B) decoder which allows the control of up to 4
independent SRAMs. The truth table for these inputs is shown in Table 2.
Table 2.
Truth table
Inputs
E
B
A
H
X
X
L
L
L
L
L
H
L
H
L
L
H
H
E1CON
H
L
H
H
H
Outputs
E2CON
H
H
L
H
H
E3CON
H
H
H
L
H
E4CON
H
H
H
H
L
Figure 6. Address-decode time
Note:
A, B
tAS
E
tEDL
tEDH
E1CON - E4CON
AI02551
During system design, compliance with the SRAM timing parameters must comprehend the
propagation delay between E1CON - E4CON.
2.2
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z300/W NVRAM
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40Z300/W and
SRAMs to be “Don't Care” once VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC = 2.0 V. The chip enable access time must be
sufficient to meet the system needs with the chip enable propagation delays included. If the
SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition
for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use.
10/25
Doc ID 5679 Rev 5
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