74LV4094 データシートの表示（PDF） - NXP Semiconductors.
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74LV4094 Datasheet PDF : 20 Pages
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Nexperia
74LV4094
8-stage shift-and-store bus register
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
40 C to 85 C
40 C to +125 C Unit
Min Typ[1] Max Min
Max
tW
pulse width
CP HIGH or LOW; see Figure 7
VCC = 2.0 V
34
9
-
41
VCC = 2.7 V
25
6
-
30
VCC = 3.0 V to 3.6 V
[2] 20
5
-
24
STR HIGH; see Figure 8
-
ns
-
ns
-
ns
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tsu
set-up time
D to CP; see Figure 9
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
CP to STR; see Figure 8
34
9
-
41
25
6
-
30
[2] 20
5
-
24
-
25
-
-
22
9
-
26
16
6
-
19
[2] 13
5
-
15
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
th
hold time
D to CP; see Figure 9
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
CP to STR; see Figure 8
-
50
-
-
43
17
-
51
31
13
-
38
[2] 25
10
-
30
-
10
-
-
5
4
-
+5
5
3
-
+5
[2] 5
2
-
+5
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
fmax
maximum
CP; see Figure 7
frequency
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
-
25
-
-
5
9
-
+5
5
6
-
+5
[2] 5
5
-
+5
14
52
-
12
19
70
-
16
24
87
-
20
[2]
-
95
-
-
-
ns
-
ns
-
ns
-
ns
-
MHz
-
MHz
-
MHz
-
MHz
74LV4094
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 March 2016
© Nexperia B.V. 2017. All rights reserved
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