74LV4094 データシートの表示（PDF） - NXP Semiconductors.
部品番号
コンポーネント説明
メーカー
74LV4094 Datasheet PDF : 20 Pages
| |||
Nexperia
74LV4094
8-stage shift-and-store bus register
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
40 C to 85 C
40 C to +125 C Unit
Min Typ[1] Max Min
Max
tpd
propagation CP to QS1; see Figure 7
delay
VCC = 1.2 V
[3]
-
90
-
-
VCC = 2.0 V
-
31
58
-
VCC = 2.7 V
-
23
43
-
VCC = 3.0 V to 3.6 V
[2]
-
17
34
-
VCC = 3.3 V; CL = 15 pF
-
14
-
-
CP to QS2; see Figure 7
[3]
-
ns
70
ns
51
ns
41
ns
-
ns
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
CP to QPn; see Figure 7
-
80
-
-
-
27
51
-
-
20
38
-
-
14
30
-
[2]
-
13
-
-
[3]
-
ns
61
ns
45
ns
36
ns
-
ns
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
STR to QPn; see Figure 8
-
115
-
-
-
39
75
-
-
29
55
-
[2]
-
22
44
-
-
18
-
-
[3]
-
ns
90
ns
66
ns
53
ns
-
ns
VCC = 1.2 V
-
105
-
-
VCC = 2.0 V
-
36
68
-
VCC = 2.7 V
-
26
50
-
VCC = 3.0 V to 3.6 V
[2]
-
20
40
-
VCC = 3.3 V; CL = 15 pF
-
17
-
-
ten
enable time OE to QPn; see Figure 10
[4]
VCC = 1.2 V
-
100
-
-
VCC = 2.0 V
-
34
65
-
VCC = 2.7 V
-
25
48
-
VCC = 3.0 V to 3.6 V
[2]
-
19
38
-
tdis
disable time OE to QPn; see Figure 10
[5]
VCC = 1.2 V
-
65
-
-
VCC = 2.0 V
-
24
40
-
VCC = 2.7 V
-
18
32
-
VCC = 3.0 V to 3.6 V
[2]
-
14
26
-
-
ns
82
ns
60
ns
48
ns
-
ns
-
ns
77
ns
56
ns
45
ns
-
ns
49
ns
37
ns
30
ns
74LV4094
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 March 2016
© Nexperia B.V. 2017. All rights reserved
8 of 20
Share Link: 