74LV4094 データシートの表示（PDF） - NXP Semiconductors.
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74LV4094 Datasheet PDF : 20 Pages
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Nexperia
74LV4094
8-stage shift-and-store bus register
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
40 C to 85 C
40 C to +125 C Unit
Min Typ[1] Max Min
Max
CPD
power
CL = 50 pF; f = 1 MHz;
dissipation
VI = GND to VCC
capacitance
[7]
-
83
-
-
-
pF
[1] All typical values are measured at Tamb = 25 C.
[2] All typical values are measured at VCC = 3.3 V.
[3] tpd is the same as tPLH and tPHL.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPLZ and tPHZ.
[6] tt is the same as tTHL and tTLH.
[7] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveforms
9,
&3LQSXW
*1'
92+
43Q46RXWSXW
92/
IPD[
90
W:
W3/+
90
W3+/
92+
46RXWSXW
92/
W3/+
90
W3+/
DDI
Fig 7.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse
width and the maximum frequency (CP)
74LV4094
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 March 2016
© Nexperia B.V. 2017. All rights reserved
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