RX5C348A/B_95 データシートの表示（PDF） - RICOH Co.,Ltd.

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RX5C348A/B_95

4-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION

RICOH Co.,Ltd. 

R×5C348A/B

2.2-6 CTFG

Periodic Interrupt Flag Bit

CTFG

Description

0

Periodic interrupt output “H” (OFF)

(Default setting)

1

Periodic interrupt output “L” (ON)

The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). The CTFG bit

accepts only the writing of 0 in the level mode, which disables (“H”) the INTR pin until it is enabled (“L”) again in

the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

2.2-7 WAFG and DAFG

Alarm_W Flag Bit and Alarm_D Flag Bit

WAFG, DAFG

Description

0

Indicating a mismatch between current time and preset alarm time

(Default setting)

1

Indicating a match between current time and preset alarm time

The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused

approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers

and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTR

pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1

causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled

with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output

of the INTR pin as shown in the timing chart below.

Output Relationships Between the WAFG or DAFG Bit and INTR

Approx.61µs

Approx.61µs

Settings of WAFG (DAFG) bit

Output of INTR pin

Writing of 0 to WAFG

(DAFG) bit

Writing of 0 to WAFG

(DAFG) bit

(Match between current time (Match between current time (Match between current time

and preset alarm time)

and preset alarm time)

and preset alarm time)

16

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