CY7C4282V データシートの表示（PDF） - Cypress Semiconductor

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CY7C4282V

Low Voltage 128K x 9 Deep Sync FIFO

Cypress Semiconductor 

CY7C4282V

CY7C4292V

Pin Definitions

Signal Name

D0−8

Q0−8

WEN

Description

Data Inputs

Data Outputs

Write Enable

REN

Read Enable

WCLK

Write Clock

RCLK

Read Clock

EF

FF

PAE

PAF/XO

FL/RT

Empty Flag

Full Flag

Programmable

Almost Empty

Programmable

Almost Full/

Expansion

Output

First Load/

Retransmit

XI/LD

OE

RS

Expansion In-

put/Load

Output Enable

Reset

I/O

Description

I Data Inputs for 9-bit bus.

O Data Outputs for 9-bit bus.

I The only write enable when device is configured to have programmable flags. Data is

written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.

I Enables the device for Read operation. REN must be asserted LOW to allow a Read

operation.

I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.

When LD is asserted, WCLK writes data into the programmable flag-offset register.

I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.

When LD is LOW, RCLK reads data out of the programmable flag-offset register.

O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-

grammed into the FIFO. PAE is synchronized to RCLK.

O Dual-Mode Pin:

Cascaded - Connected to XI of next device.

Not Cascaded - When PAF is LOW, the FIFO is almost full based on the almost full offset value

programmed into the FIFO. PAF is synchronized to WCLK.

I Dual-Mode Pin:

Cascaded - The first device in the daisy chain will have FL tied to VSS; all other devices

will have FL tied to VCC. In standard mode or width expansion, FL is tied to VSS

on all devices.

Not Cascaded - Retransmit function is available in stand-alone mode by strobing

RT.

I Dual-Mode Pin:

Cascaded - Connected to XO of previous device.

Not Cascaded - LD is used to write or read the programmable flag offset registers. LD

must be asserted LOW during reset to enable standalone or width expansion operation.

If programmable offset register access is not required, LD can be tied to RS directly.

I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connect-

ed. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

I Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ....................................... −65°C to +150°C

Ambient Temperature with

Power Applied .................................................... −55°C to +125°C

Supply Voltage to Ground Potential..........−0.5V to VCC +0.5V

DC Voltage Applied to Outputs

in High Z State ..............................................−0.5V to VCC+0.5V

DC Input Voltage .........................................−0.5V to VCC +0.5V

Output Current into Outputs (LOW) ............................. 20 mA

Static Discharge Voltage ........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current ..................................................... >200 mA

Operating Range

Range

Commercial

Industrial[1]

Ambient

Temperature

0°C to +70°C

−40°C to +85°C

VCC [2]

3.3V + /−300mV

3.3V + /−300mV

Notes:

1. TA is the “instant on” case temperature.

2. VCC Range for commercial -10 ns is 3.3V ± 150 mV.

3

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