IN74ACT192N データシートの表示（PDF） - IK Semicon Co., Ltd

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IN74ACT192N

Presettable BCD/Decade UP/DOWN Counter High-Speed Silicon-Gate CMOS

IK Semicon Co., Ltd 

IN74ACT192

TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V ± 10%)

Symbol

Parameter

tsu

Minimum Setup Time, Pn to PL (Figure 7)

th

Minimum Hold Time, PL to Pn (Figure 7)

tw

Minimum Pulse Width, PL (Figure 4)

tw

Minimum Pulse Width, CPU or CPD

(Figure 1)

tw

Minimum Pulse Width, MR (Figure 5)

trec

Minimum Recovery Time, PL to CPU or CPD (Figure

5)

trec

Minimum Recovery Time, MR to CPU or CPD

(Figure 5)

Guaranteed Limits

25 °C

-40°C to

Unit

85°C

8

9

ns

-1.0

-1.0

ns

14

15

ns

10

11

ns

12

14

ns

8

9

ns

14

16

ns

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

Figure 4. Switching Waveforms

Rev. 00

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