CY7C1486BV33 データシートの表示（PDF） - Cypress Semiconductor
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CY7C1486BV33 Datasheet PDF : 36 Pages
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Truth Table
The truth table for CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 follows.[2, 3, 4, 5, 6]
Operation
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Sleep mode, power-down
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Read cycle, begin burst
Read cycle, begin burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Read cycle, continue burst
Write cycle, continue burst
Write cycle, continue burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Read cycle, suspend burst
Write cycle, suspend burst
Write cycle, suspend burst
Add. Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
H X XL X
L
X
X
X L-H Tri-state
L L XL L
X
X
X
X L-H Tri-state
L X HL L
X
X
X
X L-H Tri-state
L L XL H
L
X
X
X L-H Tri-state
L X HL H
L
X
X
X L-H Tri-state
X X XH X
X
X
X
X X Tri-state
L H LL L
X
X
X
L L-H Q
L H LL L
X
X
X
H L-H Tri-state
L H LL H
L
X
L
X L-H D
L H LL H
L
X
H
L L-H Q
L H LL H
L
X
H H L-H Tri-state
X X XL H
H
L
H
L L-H Q
X X XL H
H
L
H H L-H Tri-state
H X XL X
H
L
H
L L-H Q
H X XL X
H
L
H H L-H Tri-state
X X XL H
H
L
L
X L-H D
H X XL X
H
L
L
X L-H D
X X XL H
H
H
H
L L-H Q
X X XL H
H
H
H
H L-H Tri-state
H X XL X
H
H
H
L L-H Q
H X XL X
H
H
H
H L-H Tri-state
X X XL H
H
H
L
X L-H D
H X XL X
H
H
L
X L-H D
Notes
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a do not care for
the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-15145 Rev. *F
Page 11 of 36
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