ISP1583 データシートの表示（PDF） - NXP Semiconductors.
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ISP1583 Datasheet PDF : 100 Pages
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NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Table 3. Pin description …continued
Symbol[1] Pin
Type[2] Description
ISP1583BS ISP1583ET; ISP1583ET1
ISP1583ET2
DACK
10
F1
E2
I/O DMA acknowledge input or output (programmable
polarity); the signal direction depends on bit MASTER in
register DMA Hardware (see Table 59):
• Input: DMA slave mode if bit MASTER = 0
• Output: DMA master mode if bit MASTER = 1
When not in use, in the default setting, this pin must be
connected to VCC(I/O) through a 10 kΩ resistor.
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DIOR
11
G2
E3
I/O DMA read strobe input or output (programmable polarity);
the signal direction depends on bit MASTER in register
DMA Hardware (see Table 59):
• Input: DMA slave mode if bit MASTER = 0
• Output: DMA master mode if bit MASTER = 1
When not in use, in the default setting, this pin must be
connected to VCC(I/O) through a 10 kΩ resistor.
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DIOW
12
G1
F1
I/O DMA write strobe input or output (programmable polarity);
the signal direction depends on bit MASTER in register
DMA Hardware (see Table 59):
• Input: DMA slave mode if bit MASTER = 0
• Output: DMA master mode if bit MASTER = 1
When not in use, in the default setting, this pin must be
connected to VCC(I/O) through a 10 kΩ resistor.
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DGND
13
H2
F2
-
digital ground
INTRQ 14
H1
G2
I
interrupt request input; from the ATA/ATAPI peripheral; use
a 10 kΩ resistor to pull down
input pad; TTL; 5 V tolerant
READY/ 15
J1
IORDY
G1
I/O Signal ready output — Used in generic processor mode:
• LOW: the ISP1583 is processing a previous command
or data and is not ready for the next command or data
transfer
• HIGH: the ISP1583 is ready for the next
microprocessor read or write
I/O ready input — Used in split bus mode to access
ATA/ATAPI peripherals (PIO mode only)
bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant
INT
16
K1
H1
O
interrupt output; programmable polarity (active HIGH or
LOW) and signaling (edge or level triggered)
CMOS output; 8 mA drive
DA2[3]
17
J2
H2
O
address output to select the Task File register of an
ATA/ATAPI device; see Table 61
CMOS output; 8 mA drive
CS_N
18
K2
E4
I
chip selection input
input pad; TTL; 5 V tolerant
ISP1583_7
Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
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