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82562G データシートの表示(PDF) - Intel

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82562G Datasheet PDF : 44 Pages
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Networking Silicon — 82562G
3.0
Performance Enhancements
3.1
New Usage Modes: 1, 2, 3, and 4
82562G supports several new features that offer design flexibility and reduced BOM cost
compared to the 82562ET PLC device. To implement these new features, a board design must
include the proper pull-up and/or pull-down strapping resistor options. Refer to the 82562GT/
82562GZ/82562GX/82562G LAN on Motherboard Design Guide for more information. Table 3
lists the four new modes.
Table 3. Usage Modes 1, 2, 3, and 4
Mode
Benefit
Mode 0: 82562ET compatible.
Mode 1: LED configuration B and single-
pin LAN disable.
No BOM changes necessary for equivalent performance to
82562ET.
Usability and reduced BOM cost.
Mode 2: Same as mode 1, except LED
configuration C.
Mode 3: LED configuration B, Single Pin
LAN Disable, and enhanced Tx modea
Mode 4: Same as mode 3, except LED
configuration C.
See table note a.
Usability and reduced BOM cost.
Usability, reduced BOM cost, and stronger Tx drive strength.
Refer to Section 3.1.2.
Usability, reduced BOM cost, and stronger Tx drive strength.
Refer to Section 3.1.2.
a. Only use this mode if advised to do so by an Intel representative to compensate for board design issues affecting IEEE
compliance.
3.1.1
Pin Usage for Modes 1, 2, 3, and 4
To use modes 1, 2, 3, or 4, the following pins need to be reviewed (refer to Table 1):
ISOL_TCK
ISOL_TI
ISOL_EX
TESTEN
ADV10/LAN_DISABLE# and supporting circuits
ACTLED#, SPDLED#, and LILED# and supporting circuits
Datasheet
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