IDT71V416L データシートの表示（PDF） - Integrated Device Technology

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IDT71V416L

3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)

Integrated Device Technology 

IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)

ADDRESS

CS

BHE, BLE

tWC

tAW

tAS

tCW (2)

tBW

tWP

tWR

WE

DATAOUT

DATAIN

tDH

tDW

DATAIN VALID

3624 drw 09

Timing Waveform of Write Cycle No. 3

(BHE, BLE Controlled Timing)(1,3)

ADDRESS

CS

BHE, BLE

tWC

tAW

tCW (2)

tAS

tBW

tWP

tWR

WE

DATAOUT

DATAIN

tDW

tDH

DATAIN VALID

3624 drw 10

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. During this period, I/O pins are in the output state, and input signals must not be applied.

3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6.742

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