ICD2025 データシートの表示（PDF） - Cypress Semiconductor
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ICD2025 Datasheet PDF : 7 Pages
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ICD2025
Features
D Three independent clock outputs:
separate CPUCLK, SYSCLK and
Buffered Reference Clock
D Ideally suited for 386/486
motherboard applications
D PhaseĆlocked loop output range of
1.843 MHz - 100 MHz
D PhaseĆlocked loop oscillator input
derived from single 14.31818 MHz
crystal
D Sophisticated internal loopĆfilter
requires no external components or
manufacturing tweaks as commonly
required with external filters
Motherboard Clock Generator
D ThreeĆstate oscillator control disables
outputs for test purposes
D 5V operation
D LowĆpower, highĆspeed CMOS
technology
D Available in 16Ćpin SOIC package
Functional Description
A modern personal computer motherĆ
board often requires many different
crystal can oscillators. The System Logic
family of frequency synthesis parts from
Cypress/IC Designs replaces the large
number of oscillators required to build
such multiĆfunction motherboards. These
parts synthesize all the required frequenĆ
cies in a single monolithic device, thus
lowering manufacturing costs and signifiĆ
cantly reducing the printed circuit borad
space required.
The ICD2025 is a lowĆcost approach to
the generation of the 3 necessary clocks
required by any PC motherboard.
Logic Block Diagram
fXRTEAF/LIN
XTALOUT
n DPehteacsteor
7
ROM
7
C0
CCC123
S0
SS12
PLL #2
Charge
Pump
VCO
Internal Loop Filter
m PhaseĆLocked Loop
Oscillator #1
SYSBUS
14.318 MHz
CPUCLK
SYSCLK
GND VDD AVDD
OE
ICD2025Ć2
Pin Configuration
SYSBUS
SYSCLK
OE
GND
fREF/XTALIN
XTALOUT
C0
S0
SOIC
Top View
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
AVDD
CPUCLK
C3
VDD
S2
C2
C1
S1
ICD2025Ć1
Cypress Semiconductor Corporation
D
3901 North First Street
1
D D San Jose
CA 95134
D
408-943-2600
August, 1994 - Revised April 1995
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