8405202XA データシートの表示（PDF） - Intersil

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8405202XA

CMOS 16-Bit Microprocessor

Intersil 

Waveforms (Continued)

80C86

AC Test Circuit

≥ 50µs

VCC

CLK

(7) TCLDX1

(6) TDVCL

RESET

≥ 4 CLK CYCLES

FIGURE 13. RESET TIMING

OUTPUT FROM

DEVICE UNDER TEST

TEST POINT

CL (SEE NOTE)

NOTE: Includes stay and jig capacitance.

AC Testing Input, Output Waveform

INPUT

VIH + 20% VIH

1.5V

VIL - 50% VIL

OUTPUT

1.5V

VOH

VOL

NOTE: AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between

0.4V and VCC.-0.4 Input rise and fall times are driven at 1ns/V.

3-167

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