ISP1562 データシートの表示（PDF） - NXP Semiconductors.

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ISP1562

Hi-Speed USB PCI host controller

NXP Semiconductors. 

NXP Semiconductors

ISP1562

HS USB PCI host controller

16.1 Timing

Table 124. PCI clock and IO timing

VCC(I/O) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PCI clock timing; see Figure 7

Tcyc(PCICLK)

PCICLK cycle time

tHIGH(PCICLK)

PCICLK HIGH time

tLOW(PCICLK)

PCICLK LOW time

SRPCICLK

PCICLK slew rate

SRRST#

RST# slew rate

PCI input timing; see Figure 8

30

-

11

-

11

-

1

-

50

-

32

ns

-

ns

-

ns

4

V/ns

-

mV/ns

tsu(PCICLK)bs

tsu(PCICLK)ptp

set-up time to PCICLK (bus signal)

set-up time to PCICLK

(point-to-point)

7

-

-

ns

[1] 10

-

-

ns

th(PCICLK)

input hold time from PCICLK

PCI output timing; see Figure 9

0

-

-

ns

tval(PCICLK)bs

PCICLK to signal valid delay (bus

signal)

2

-

11

ns

tval(PCICLK)ptp

PCICLK to signal valid delay

(point-to-point)

[1] 2

-

12

ns

tdZ(act)

float to active delay

td(act)Z

active to float delay

PCI reset timing

2

-

-

-

-

ns

28

ns

trst

trst-clk

reset active time after power stable

reset active time after CLK stable

1

-

-

ms

100

-

-

µs

[1] REQ# and GNT# are point-to-point signals. GNT# has a set up of 10 ns; REQ# has a set up of 12 ns. All others are bus signals.

0.6VCC(I/O)

0.5VCC(I/O)

0.4VCC(I/O)

0.3VCC(I/O)

0.2VCC(I/O)

Fig 7. PCI clock

Tcyc(PCICLK)

tHIGH(PCICLK)

tLOW(PCICLK)

minimum value

0.4VCC(I/O)

004aaa604

ISP1562_3

Product data sheet

Rev. 03 — 14 November 2008

© NXP B.V. 2008. All rights reserved.

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