UPD720102 データシートの表示（PDF） - NEC => Renesas Technology
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UPD720102 Datasheet PDF : 36 Pages
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μPD720102
AC Characteristics (VDD = 3.135 to 3.465 V, TA = −20 to +70°C)
System clock ratings
Parameter
Clock frequency
Clock duty cycle
Symbol
fCLK
Condition
Crystal
Oscillator block
tDUTY
Min.
Typ.
Max.
Unit
−500
30
+500
MHz
ppm
ppm
−500
48
+500
MHz
ppm
ppm
40
50
60
%
Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm.
2. Required accuracy of crystal or oscillator block is including initial frequency accuracy, the spread of
crystal capacitor loading, supply voltage, temperature, and aging, etc.
PCI interface block
Parameter
Symbol
Condition
<R> PCI clock cycle time
tcyc
PCI clock pulse, high-level width
thigh
PCI clock pulse, low-level width
tlow
PCI clock, rise slew rate
Scr
0.2VDD to 0.6VDD
PCI clock, fall slew rate
Scf
0.2VDD to 0.6VDD
PCI reset active time (vs. power supply stability) trst
PCI reset active time (vs. CLK start)
Output float delay time (vs. RST0↓)
trst-clk
trst-off
PCI reset rise slew rate
Srr
PCI bus signal output time (vs. PCLK↑)
tval
PCI point-to-point signal output time (vs. PCLK↑)
Output delay time (vs. PCLK↑)
tval (ptp)
ton
REQ0
Output float delay time (vs. PCLK↑)
toff
Input setup time (vs. PCLK↑)
tsu
Point-to-point input setup time (vs. PCLK↑)
tsu (ptp) GNT0
Input hold time
th
Min.
Max.
Unit
30
33
ns
11
ns
11
ns
1
4
V/ns
1
4
V/ns
1
ms
100
μs
40
ns
50
mV/ns
2
11
ns
2
12
ns
2
ns
28
ns
7
ns
10
ns
0
ns
22
Data Sheet S17998EJ4V0DS
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