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PCI output timing measurement condition
PCLK
Output delay
0.4VDD
tval , tval (ptp)
0.615VDD (for falling edge)
0.285VDD (for falling edge)
µPD720101
0.6VDD
0.2VDD
Output
ton
toff
PCI input timing measurement condition
PCLK
Input
0.4VDD
tsu , tsu (ptp)
th
0.6VDD
0.2VDD
0.6VDD
0.4VDD
0.2VDD
Data Sheet S16265EJ4V0DS
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