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Timing Diagram
PCI Clock
0.6VDD
0.5VDD
0.4VDD
0.3VDD
0.2VDD
PCI Reset
PCLK
PWR_GOOD
VBBRST0
tcyc
thigh
tlow
100 ms (typ.)
trst-clk
trst
PCI Signals
PCI Output Timing Measurement Condition
PCLK
output
delay
0.4VDD
tval , tval(ptp)
0.615VDD(for falling edge)
0.285VDD(for falling edge)
output
ton
toff
µPD720100A
0.4VDD(ptp:min)
Valid
trst-off
0.6VDD
0.2VDD
Data Sheet S15535EJ2V0DS
23