AOZ1033AI データシートの表示（PDF） - Alpha and Omega Semiconductor
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AOZ1033AI Datasheet PDF : 15 Pages
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AOZ1033AI
Detailed Description
The AOZ1033A is a current-mode step down regulator
with integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5V to 18V input volt-
age range and supplies up to 3A of load current. The
duty cycle can be adjusted from 6% to 100% allowing a
wide range of output voltage. Features include enable
control, Power-On Reset, input under voltage lockout,
output over voltage protection, active high power good
state, fixed internal soft-start and thermal shut down.
The AOZ1033A is available in SO-8 package.
Enable and Soft Start
The AOZ1033A has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In soft start process, the output volt-
age is ramped to regulation voltage in typically 2.2ms.
The 2.2ms soft start time is set internally.
The EN pin of the AOZ1033A is active high. Connect the
EN pin to VIN if enable function is not used. Pull it to
ground will disable the AOZ1033A. Do not leave it open.
The voltage on EN pin must be above 2V to enable the
AOZ1033A. When voltage on EN pin falls below 0.6V, the
AOZ1033A is disabled. If an application circuit requires
the AOZ1033A to be disabled, an open drain or open col-
lector circuit should be used to interface to EN pin.
Steady-State Operation
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1033A integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error volt-
age, which shows on the COMP pin, is compared against
the current signal, which is sum of inductor current signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
high-side switch is off. The inductor current is freewheel-
ing through the internal low-side N-MOSFET switch to
output. The internal adaptive FET driver guarantees no
turn on overlap of both high-side and
low-side switch.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1033A uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
The AOZ1033A will enter the discontinuous conduction
mode at light load. Several pulses may be skipped in
between switching cycles at very light load, it further
improving light load efficiency.
The AOZ1033A uses a P-Channel MOSFET as the
high-side switch. It saves the bootstrap capacitor nor-
mally seen in a circuit which is using an NMOS switch. It
allows 100% turn-on of the high-side switch to achieve
linear regulation mode of operation. The minimum volt-
age drop from VIN to VO is the load current times DC
resistance of MOSFET plus DC resistance of buck induc-
tor. It can be calculated by equation below:
VO_MAX = VIN – IO × RDS(ON)
where;
VO_MAX is the maximum output voltage;,
VIN is the input voltage from 4.5V to 18V,
IO is the output current from 0A to 3A, and
RDS(ON) is the on resistance of internal MOSFET. The value is
between 97mΩ and 200mΩ depending on input voltage and
junction temperature.
Switching Frequency
The AOZ1033A switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 500kHz to 700kHz due to device varia-
tion.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
VO
=
0.8
×
⎛
⎜1
+
R-----1-⎟⎞
⎝ R2⎠
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1 on the next page.
Rev. 1.1 October 2010
www.aosmd.com
Page 7 of 15
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