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LC863540B データシートの表示(PDF) - SANYO -> Panasonic

部品番号
コンポーネント説明
一致するリスト
LC863540B
SANYO
SANYO -> Panasonic SANYO
LC863540B Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC863548B/40B/32B/28B/24B/20B/16B
Sub-routine stack level
A maximum of 128 levels (stack is built in the internal RAM)
Multiplication/division instruction
16-bits × 8-bits (7 instruction cycle times)
16-bits ÷ 8-bits (7 instruction cycle times)
3 oscillation circuits
Built-in RC oscillation circuit used for the system clock
Built-in VCO circuit used for the system clock and OSD
X’tal oscillation circuit used for base timer, system clock and PLL reference
Standby function
HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.
HOLD mode
The HOLD mode is used to stop the oscillations ; RC (internal), VCO, and X’tal oscillations.
This mode can be released by the following conditions.
1. Pull the reset terminal (RES) to low level.
2. Feed the selected level to either P70/INT0 or P71/INT1.
Package
MFP36S
DIP36S
Development tools
Flash EEPROM
Evaluation chip
Emulator
: LC86F3548A
: LC863096
: EVA86000 (main) + ECB863200A (evaluation chip board)
+ SUB863400A (sub board)
+ POD36-CABLE (cable)
+ POD36-DIP (for DIP36S)
or POD36-MFP (for MFP36S)
No.7936-4/17

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