HI3516D データシートの表示（PDF） - Unspecified
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HI3516D Datasheet PDF : 7 Pages
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Hi3516D
Hi3516D Professional HD IP Camera SoC
Functional Block Diagram
16bit
DDR3/DDR3L
@600MHz
DDRC
SDHC/XC
SPI Nor/
Nand Flash
Nand Flash
GMAC PHY
SDIO3.0
x2
Flash I/F
Nand I/F
GMAC
USB
USB 2.0
Host/Device
Audio
CODEC
I2S
Hi3516D
ARM Subsystem
Cortex A7 @600MHz
(32K ICache/32K DCache)
Image Subsystem
TDE + IVS
VPSS+VGS
ISP
（3A\WDR）
CVBS/
BT.1120
MIPI/
LVDS/
Hispi
AMBA3.0 BUS
Video Subsystem
H264/H265 BP/MP
MJPEG/JPEG
Encoder
AES/DES/3DES
RTC
I2Cx3
SSPx4
GPIOs
IR
UARTx4
PWMx8
SAR-
ADCx2
As a new-generation SoC designed for the HD IP camera, the Hi3516D integrates a new-generation ISP and adopts the latest H.265
compressed video encoder, advanced low-power technology, and low-power architecture design. These features help the Hi3516D
keep the leading position in the aspects of low bit rate, high picture quality, and low power consumption. The Hi3516D supports 90°
or 270° rotation and lens distortion correction, which meets requirements in various surveillance applications. It also fully supports
3A algorithms, which allow customers to design different types of IP cameras including the IP AF zoom module. The Hi3516D
integrates the POR, RTC, and audio CODEC and supports various sensor levels and clock outputs, which significantly reduces the
EBOM costs for the Hi3516D HD IP camera. Similar to other HiSilicon DVR and NVR SDKs, the Hi3516D SDK features high
stability and ease of use, which allows rapid mass production and facilitates system layout of IP cameras, DVRs, and NVRs.
Issue 01 (2014-12-22)
HiSilicon Proprietary and Confidential
Copyright © HiSilicon Technologies Co., Ltd
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