GL852G データシートの表示（PDF） - Genesys Logic
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GL852G Datasheet PDF : 38 Pages
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GL852G Datasheet
Pin Name
X1
X2
RESET#
SEL48#/
SEL27#
LQFP
48 Pin
14
15
26
25,44
GL852G
QFN SSOP
28 Pin 28 Pin
10
6
11
7
17
13
--
--
Clock and Reset Interface
I/O
LQFN Type
46 Pin
Description
12
I Crystal / OSC clock input
13
O Crystal clock output.
25
24,42
Active low. External reset input, default pull high 10KΩ.
I When RESET# = low, whole chip is reset to the initial
state.
SEL48#/SEL27#:
I
0 1: 48MHz OSC-in
1 0: 27MHz OSC-in
1 1: 12MHz X’tal/OSC-in
Pin Name
TEST/SCL
SDA
LQFP
48 Pin
27
--
GL852G
QFN SSOP
28 Pin 28 Pin
18
14
26
--
System Interface
I/O
LQFN Type
46 Pin
Description
I TEST: 0: Normal operation.
26 (pd)
1: Chip will be put in test mode.
B I2C: clock output pin
-
B I2C data pin
Pin Name
AVDD
DVDD
GND
V5
V33
LQFP
48 Pin
1,7,12,
16,19
34,38
2,8,
13,20
47
48
GL852G
QFN SSOP
28 Pin 28 Pin
5,9,14 1,5,10
21
16
-
15
27
23
28
24
Power / Ground
I/O
LQFN Type
46 Pin
Description
1,6,10,
14,17
P 3.3V analog power input for analog circuits.
33
P 3.3V digital power input for digital circuits
-
P
Ground
Exposed pad is connected to GND (QFN28/ LQFN46)
45
P/I
5V Power
regulator
input.
It
need
be
NC
if
using
external
5V-to-3.3V regulator Vout (LQFP48/ LQFN46)
5V-to-3.3V regulator Vout & 3.3 input
46 P / O (QFN28/SSOP28)
It can be NC or connect to 3.3V power if using external
regulator (LQFP48/ LQFN46 only)
Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power
routing and the ground plane. For detailed information, please refer to GL85X Design Guide.
©2012 Genesys Logic, Inc. - All rights reserved.
Page 17
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