GL852G データシートの表示（PDF） - Genesys Logic
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GL852G Datasheet PDF : 38 Pages
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GL852G Datasheet
3.3 Pin Descriptions
Table 3.5 - Pin Descriptions
Pin Name
DM0,DP0
DM1,DP1
DM2,DP2
DM3,DP3
DM4,DP4
RREF
LQFP
48 Pin
3,4
5,6
9,10
17,18
21,22
11
USB Interface
GL852G
QFN SSOP
28 Pin 28 Pin
1,2 25,26
LQFN
46 Pin
2,3
I/O
Type
Description
B USB signals for USPORT
3,4 27,28 4,5
B USB signals for DSPORT1
6,7
2,3
7,8
B USB signals for DSPORT2
12,13 8,9 15,16 B USB signals for DSPORT3
15,16 11,12 18,19 B USB signals for DSPORT4
8
4
9
A
A 680Ω resister must be connected between RREF
and analog ground (AGND).
Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to
GL85X Design Guide.
Hub Interface
Pin Name
OVCUR1#~4
PWREN1#~4
GREEN1~4
AMBER1~4
PSELF
PGANG
LQFP
48 Pin
42,40,
30,28
43,41,
31,29
45,35,
32,23
46,36,
33,24
37
39
GL852G
QFN SSOP
28 Pin 28 Pin
25,24,
20,19
21,19
- 22,20
-
-
-
-
22
17
23
18
I/O
LQFN Type
46 Pin
Description
40,38,
29,27
I
(pu)
Active low. Over current indicator for DSPORT1~4
OVCUR1# is the only over current flag for GANG
mode.
41,39,
30,28
Active low. Power enable output for DSPORT1~4
O PWREN1# is the only power-enable output for
GANG mode.
43,34,
31,20
1,3,4: O
2: B
(pd)
Green LED indicator for DSPORT1~4
*GREEN[1~2] are also used to access the external
EEPROM
For detailed information, please refer to Chapter
5.
44,35,
32,21
O
(pd)
Amber LED indicator for DSPORT1~4
*Amber [1~2] are also used to access the external
EEPROM
36
I
0: GL852G is bus-powered.
1: GL852G is self-powered.
This pin is default put in input mode after power-on
reset. Individual/gang mode is strapped during this
period. After the strapping period, this pin will be
set to output mode, and then output high for normal
mode.
37
B When GL852G is suspended, this pin will output low.
*For detailed explanation, please see Chapter 5
Gang
input:1, output: 0@normal,
1@suspend
Individual input:0, output: 1@normal,
0@suspend
©2012 Genesys Logic, Inc. - All rights reserved.
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