RTL8111C-VC-GR データシートの表示（PDF） - Realtek Semiconductor

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RTL8111C-VC-GR

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS

Realtek Semiconductor 

RTL8111C

Datasheet

6.4. Next Page

If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the

two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and

Reg8 as defined in IEEE 802.3ab.

6.5. EEPROM Interface

The RTL8111C requires the attachment of an external EEPROM. The 93C46/93C56 is a 1K-bit/2K-bit

EEPROM. The EEPROM interface permits the RTL8111C to read from, and write data to, an external

serial EEPROM device.

Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be

overridden following a power-on or software EEPROM auto-load command. The RTL8111C will

auto-load values from the EEPROM. If the EEPROM is not present, the RTL8111C initialization uses

default values for the appropriate Configuration and Operational Registers. Software can read and write to

the EEPROM using bit-bang accesses via the 9346CR Register, or using PCI VPD (Vital Product Data).

The interface consists of EESK, EECS, EEDO, and EEDI.

The correct EEPROM (i.e., 93C46/93C56) must be used in order to ensure proper LAN function.

EEPROM

EECS

EESK

EEDI/Aux

EEDO

Table 11. EEPROM Interface

Description

93C46/93C56 Chip Select.

EEPROM Serial Data Clock.

Input Data Bus/Input Pin to Detect Whether Aux. Power Exists on Initial Power-On.

This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM

power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled

high to Aux. Power, the RTL8111C assumes that no Aux. Power exists.

Output Data Bus.

Integrated Gigabit Ethernet Controller for PCI Express

13

Track ID: JATR-1076-21 Rev. 1.5

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