IS61LV12824-10B データシートの表示（PDF） - Integrated Circuit Solution Inc
部品番号
コンポーネント説明
一致するリスト
IS61LV12824-10B Datasheet PDF : 10 Pages
| |||
IS61LV12824
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-9
-10
-12
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
1
tWC Write Cycle Time
8—
9—
10 —
12 —
ns
tSCE CE1, CE2 to Write End
7—
8—
8—
9—
ns
tSCE2 CE2 to Write End
7—
8—
8—
9—
2
tAW Address Setup Time
7—
8—
8—
9—
ns
to Write End
tHA Address Hold from Write End 0 —
0—
0—
0—
ns
tSA Address Setup Time
0—
0—
0—
0—
ns
3
tPWE1 WE Pulse Width (OE = HIGH) 6 —
8—
8—
9—
ns
tPWE2 WE Pulse Width (OE = LOW) 6 —
9—
9—
10 —
ns
tSD Data Setup to Write End 4.5 —
5—
5—
5—
ns
4
tHD Data Hold from Write End 0 —
0—
0—
0—
ns
t (2)
HZWE
WE LOW to High-Z Output
— 3.5
— 3.5
— 3.5
— 3.5
ns
t (2)
LZWE
WE HIGH to Low-Z Output
3
—
3—
3—
3—
ns
5
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
6
3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
WRITE CYCLE NO. 1 (WE Controlled)
7
ADDRESS
CE1, CE2
CE2
WE
DOUT
DIN
t WC
VALID ADDRESS
t SA
t SCE1
t SCE2
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
8
9
10
11
12
Integrated Circuit Solution Inc.
7
SR021-0B
Share Link: 