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IS61LV12824-9B データシートの表示(PDF) - Integrated Circuit Solution Inc

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IS61LV12824-9B
ICSI
Integrated Circuit Solution Inc ICSI
IS61LV12824-9B Datasheet PDF : 10 Pages
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IS61LV12824
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 9, 10, 12 ns
• CMOS low power operation
720 mW (typical) operating @ 9 ns
36 mW (typical) standby @ 9 ns
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Available in 119-pin 14x22mm PBGA
DESCRIPTION
The ICSI IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using ICSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When CE1, CE2 are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE1, CE2, CE2 and OE. The active
LOW Write Enable (WE) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin 14*22mm PBGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
VCC
GND
I/O0-I/O23
DECODER
I/O
DATA
CIRCUIT
128K x 24
MEMORY ARRAY
COLUMN I/O
CE2
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
SR021-0B

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