BS616UV2021AC70 データシートの表示（PDF） - Brilliance Semiconductor

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BS616UV2021AC70

Ultra Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable

Brilliance Semiconductor 

BSI

BS616UV2021

„ PIN DESCRIPTIONS

Name

A0-A16 Address Input

Function

These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.

SAE Address Input

CIO x8/x16 select input

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

D0 - D15 Data Input/Output Ports

This address input incorporates with the above 17 address input select one of the

262,144 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.

This input selects the organization of the SRAM. 131,072 x 16-bit words configuration

is selected if CIO is HIGH. 262,144 x 8-bit bytes configuration is selected if CIO is

LOW.

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read

from or write to the device. If either chip enable is not active, the device is deselected

and is in a standby power mode. The DQ pins will be in the high impedance state

when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins. The chip is deselected when

both LB and UB pins are HIGH.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

R0201-BS616UV2021

2

Revision 2.4

April 2002

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