DS2482-100(2009) データシートの表示（PDF） - Maxim Integrated

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DS2482-100
(Rev.:2009)

Single-Channel 1-Wire Master

Maxim Integrated 

Single-Channel 1-Wire Master

Write Configuration

Command Code

Command Parameter

D2h

Configuration Byte

Description

Writes a new configuration byte. The new settings take effect immediately. Note: When writing to

the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the

one’s complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.

Typical Use

Restriction

Defining the features for subsequent 1-Wire communication.

1-Wire activity must have ended before the DS2482-100 can process this command.

Error Response

Command code and parameter are not acknowledged if 1WB = 1 at the time the command code

is received and the command is ignored.

Command Duration

None. The Configuration Register is updated on the rising SCL edge of the configuration-byte

acknowledge bit.

1-Wire Activity

Read Pointer Position

Status Bits Affected

Configuration Bits Affected

None

Configuration Register (to verify write).

RST set to 0.

1WS, SPU, APU updated.

1-Wire Reset

Command Code

Command Parameter

B4h

None

Description

Generates a 1-Wire reset/presence-detect cycle (Figure 4) at the 1-Wire line. The state of the

1-Wire line is sampled at tSI and tMSP and the result is reported to the host processor through the

Status Register, bits PPD and SD.

Typical Use

Restriction

Error Response

To initiate or end any 1-Wire communication sequence.

1-Wire activity must have ended before the DS2482-100 can process this command.

Command code is not acknowledged if 1WB = 1 at the time the command code is received and

the command is ignored.

Command Duration

1-Wire Activity

Read Pointer Position

Status Bits Affected

Configuration Bits Affected

tRSTL + tRSTH + maximum 262.5ns, counted from the falling SCL edge of the command code

acknowledge bit.

Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.

Status Register (for busy polling).

1WB (set to 1 for tRSTL + tRSTH), PPD is updated at tRSTL + tMSP, SD is updated at tRSTL + tSI.

1WS and APU apply.

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