ADIS16136AMLZ(RevD) データシートの表示（PDF） - Analog Devices
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ADIS16136AMLZ Datasheet PDF : 20 Pages
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Data Sheet
OUTPUT DATA REGISTERS
Table 8. Output Data Register Formats
Register
Address Measurement
TEMP_OUT 0x02
Internal temperature
GYRO_OUT2 0x04
Gyroscope, lower 16 bits
GYRO_OUT 0x06
Gyroscope, upper 16 bits
Rotation Rate (Gyroscope)
GYRO_OUT is the primary register for gyroscope output data
and uses 16-bit twos complement format for its data. Table 9
provides the numerical format, and Table 10 provides several
examples for converting digital data into °/sec.
Table 9. GYRO_OUT Bit Descriptions
Bits
Description
[15:0] Gyroscope data; twos complement, 0.018275°/sec per
LSB, 0°/sec = 0x0000
Table 10. GYRO_OUT, Twos Complement Format
Rotation Rate Decimal Hex
Binary
+450°/sec
+24,623
0x602F 0110 0000 0010 1111
+0.03655°/sec +2
0x0002 0000 0000 0000 0010
+0.018275°/sec +1
0x0001 0000 0000 0000 0001
0°/sec
0
0x0000 0000 0000 0000 0000
−0.018275°/sec −1
0xFFFF 1111 1111 1111 1111
−0.03655°/sec −2
0xFFFE 1111 1111 1111 1110
−450°/sec
−24,623
0x9FD1 1001 1111 1101 0001
The GYRO_OUT2 register (see Table 11) captures the bit growth
associated with the decimation and FIR filters that are shown in
Figure 18 using a MSB justified format. The bit growth starts
with the MSB (GYRO_OUT2[15]), is equal to the decimation
rate setting in DEC_RATE[4:0] (see Table 18), and grows in the
LSB direction as the decimation rate increases. See Figure 14 for
more details.
Table 11. GYRO_OUT2 Bit Descriptions
Bits
Description
[15:0] Rotation rate data; resolution enhancement bits
D
D = DEC_RATE[4:0]
GYROSCOPE DATA
NOT USED
15
GYRO_OUT
0 15
GYRO_OUT2
0
0.018275 °/sec
BIT WEIGHT = 2D LSB LSB = GYRO_OUT2[16-D]
Figure 14. Gyroscope Output Format, DEC_RATE[4:0] > 0
Internal Temperature
The TEMP_OUT register (see Table 12) provides an internal
temperature measurement that can be useful for observing
relative temperature changes in the environment. Table 13
provides several coding examples for converting the 16-bit
twos complement number into units for temperature (°C).
ADIS16136
Table 12. TEMP_OUT Bit Descriptions
Bits
Description
[15:0] Temperature data; twos complement, 0.010697°C per
LSB, 0°C = 0x0000
Table 13. Temperature, Twos Complement Format
Temperature Decimal Hex
Binary
+85°C
+7946
0x1F0A 0001 1111 0000 1010
+0.021394°C +2
0x0002 0000 0000 0000 0010
+0.010697°C +1
0x0001 0000 0000 0000 0001
0°C
0
0x0000 0000 0000 0000 0000
−0.010697 °C −1
0xFFFF 1111 1111 1111 1111
−0.021394°C −2
0xFFFE 1111 1111 1111 1110
−40°C
−3739
0xF165 1111 0001 0110 0101
DEVICE CONFIGURATION
The control registers listed in Table 14 provide a variety of user
configuration options. The SPI provides access to these registers,
one byte at a time, using the bit assignments shown in Figure 13.
Each register has 16 bits, wherein Bits[7:0] represent the lower
address and Bits[15:8] represent the upper address.
Figure 15 provides an example of writing 0x03 to Address 0x22
(DEC_RATE[7:0]), using Pin 5, DIN = 0xA203. This example
reduces the sample rate by a factor of 8 (see Table 16).
CS
SCLK
DIN
DIN = 1010 0010 0000 0011 = 0xA203, WRITES 0x03 TO ADDRESS 0x22
Figure 15. SPI Sequence for Setting the Decimate Rate to 8 (DIN = 0xA203)
Dual Memory Structure
Writing configuration data to a control register updates its SRAM
contents, which are volatile. After optimizing each relevant control
register setting in a system, set GLOB_CMD[3] = 1 (DIN =
0xA808) to backup these settings in the nonvolatile flash memory.
The flash back up process requires a valid power supply level for
the entire 72 ms process time. Table 14 provides a user register
memory map that includes a column of flash backup information.
A “yes” in this column indicates that a register has a mirror location
in flash and, when backed up properly, automatically restores itself
during startup or after a reset. Figure 16 provides a diagram of the
dual memory structure that is used to manage operation and store
critical user settings.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
Figure 16. SRAM and Flash Memory Diagram
Rev. D | Page 9 of 20
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