ACS8515P データシートの表示（PDF） - Semtech Corporation

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ACS8515P

Line Card Protection Switch for SONET or SDH Network Elements

Semtech Corporation 

ADVANCED COMMUNICATIONS

ACS8515 Rev2.1 LC/P

Line Card Protection Switch

for SONET or SDH Network Elements

FINAL

Description

The ACS8515 is a highly integrated, single-chip

solution for ‘hit-less’ protection switching of SEC

clocks from Master and Slave SETS clockcards

in a SONET or SDH Network Element. The

ACS8515 has fast activity monitors on the in-

puts and will implement automatic system pro-

tection switching against master clock failure.

A further input is provided for an optional standby

SEC clock. The ACS8515 is fully compliant with

the required specifications and standards.

The ACS8515 can perform frequency translation

from a SEC input clock distributed along a back

plane to a different local line card clock, e.g.

8 kHz distributed on the back plane and

19.44 MHz generated on the line cards.

An SPI(1) compatible serial port is incorporated,

providing access to the configuration and status

registers for device setup.

The ACS8515 can utilise either a low cost XO

oscillator module, or a TCXO with full tempera-

ture calibration - as required by the application.

Rev2.1 adds choice of edge alignment for 8kHz

input, as well as a low jitter n x E1/DS1 output

mode. Other minor changes are made, with all

described in Appendix A.

Block Diagram

Figure 1. Simple Block Diagram

Features

•Suitable for Stratum 3, 4E and 4 SONET

or SDH Equipment Clock (SEC) applications

•Meets AT&T, ITU-T, ETSI and Telcordia

specifications

•Three SEC input clocks, from 2 kHz to

155.52 MHz

•Generates two SEC output clocks, up to

311.04 MHz

•Frequency translation of SEC input clock to a

different local line card clock

•Robust input clock source frequency and

activity monitoring on all inputs

•Supports Free-run, Locked and Holdover

modes of operation

•Automatic ‘hit-less’ source switchover on loss

of input

•External force fast switch between SEC inputs

•Phase build out for output clock phase

continuity during input switchover

•SPI(1) compatible serial microprocessor interface

•Programmable wander and jitter tracking

attenuation 0.1 Hz to 20 Hz

•Single +3.3 V operation. +5 V I/O compatible

•Operating temperature (ambient) -40°C to

+85°C

•Available in 64 pin LQFP package

•Lead (pb)-free version available (ACS8515

Rev2.1T) RoHS and WEEE compliant.

(1) SPI is a trademark of Motorola Corporation

3 x SEC Input

Master/Slave

+ Standby:

N x 8kHz

1.544/2.048MHz

6.48MHz

19.44MHz

38.88MHz

51.84MHz

77.76MHz

155.52MHz

MFrSync

3xSEC

Input

Ports

MFrSync

Monitors

DPLL

Frequency Synthesis

APLL

Frequency

Dividers

2xSEC

Output

Ports

FrSync

MFrSync

Chip Clock

Generator

Priority

Table

Register

Set

SPI Compatible Serial

Microprocessor Port

TCXO or XO

Revision 2.01/December 2005 Semtech Corp.

www.semtech.com

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