MT9094AP データシートの表示（PDF） - Zarlink Semiconductor Inc

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MT9094AP

ISO2-CMOS ST-BUS™ FAMILY Digital Telephone (DPhone-II)

Zarlink Semiconductor Inc 

MT9094

Data Sheet

On power-up reset (PWRST) or with a software reset (RST), the DATA1 pin becomes a bidirectional

(transmit/receive) serial port while the DATA2 pin is internally disconnected and tri-stated.

All data transfers through the microport are two-byte transfers requiring the transmission of a Command/Address

byte followed by the data byte written or read from the addressed register. CS must remain asserted for the

duration of this two-byte transfer. As shown in Figure 5, the falling edge of CS indicates to the DPhone-II that a

microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to

receive the Command/Address byte from the microcontroller. The Command/Address byte contains information

detailing whether the second byte transfer will be a read or a write operation and of what address. The next 8 clock

cycles are used to transfer the data byte between the DPhone-II and the microcontroller. At the end of the two-byte

transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of

DATA1 which will remain tri-stated as long as CS is high.

Receive data is sampled and transmit data is made available on DATA1 concurrent with the falling edge of SCLK.

Lastly, provision is made to separate the transmit and receive data streams onto two individual pins. This control is

given by the DATASEL pin in the General Control Register (address 0Fh). Setting DATASEL logic high will cause

DATA1 to become the data receive pin and DATA2 to become the data transmit pin. Only the signal paths are

altered by DATASEL; internal timing remains the same in both cases. Tri-stating on DATA2 follows CS as it does on

DATA1 when DATASEL is logic low. Use of the DATASEL bit is intended to help in adapting Motorola (SPI) and

National Semiconductor (Micro-wire) microcontrollers to the DPhone-II. Note that whereas Intel processor serial

ports transmit data LSB first other processor serial ports, including Motorola, transmit data MSB first. It is the

responsibility of the microcontroller to provide LSB first data to the DPhone-II.

COMMAND/ADDRESS (5) ✈✑✉ DATA INPUT/OUTPUT

✈✑✉ ✈✔✉COMMAND/ADDRESS

DATA 1

Receive

D0 D1 D2 D3 D4 D5 D6 D7

DATA 1 or DATA 2

Transmit

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

SCLK (2)

CS

✈✔✉

✈✓ ✉

✈✓ ✉

✈✑✉Delays due to MCS-51 internal timing which are transparent.

✈✒✉The DPhone-II: -latches received data on the falling edge of SCLK

-outputs transmit data on the falling edge of SCLK

✈✓✉The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent

byte is always data followed by CS returning high.

✈✔✉A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

✈✕✉The COMMAND/ADDRESS byte contains:

1 bit - Read/Write

6 bits - Addressing Data

1 bit - Not used, write logic "0"

D7

D0

0

A5 A4 A3

A2 A1

A0 R/W

Figure 5 - Serial Port Relative Timing

ST-BUS/Timing Control

A serial link is required for the transport of data between the DPhone-II and the external digital transmission device.

The DPhone-II utilizes the ST-BUS architecture defined by Zarlink Semiconductor. Refer to Zarlink Application Note

11

Zarlink Semiconductor Inc.

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