510KCA60M0000AAG データシートの表示（PDF） - Silicon Laboratories

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510KCA60M0000AAG

CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ

Silicon Laboratories 

Si510/511

Table 4. Output Clock Jitter and Phase Noise (LVPECL)

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Period Jitter

(RMS)

JPRMS

10k samples1

—

—

1.3

ps

Period Jitter

(Pk-Pk)

JPPKPK

10k samples1

—

—

11

ps

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

—

0.31

0.5

ps

bandwidth2 (brickwall)

Phase Noise,

156.25 MHz

12 kHz to 20 MHz integration band-

—

width2 (brickwall)

φN

100 Hz

—

1 kHz

—

0.8

–86

–109

1.0

ps

—

dBc/Hz

—

dBc/Hz

10 kHz

—

–116

—

dBc/Hz

100 kHz

—

–123

—

dBc/Hz

Additive RMS

Jitter Due to

External Power

Supply Noise3

JPSR

1 MHz

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

—

–136

—

dBc/Hz

—

3.0

—

ps

—

3.5

—

ps

—

3.5

—

ps

Spurious

SPR

1 MHz sinusoidal noise

LVPECL output, 156.25 MHz,

offset>10 kHz

—

3.5

—

ps

—

–75

—

dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).

6

Rev. 1.4

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