DA28F320J5-100 データシートの表示（PDF） - Intel

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DA28F320J5-100

INTEL® StrataFlash™ MEMORY TECHNOLOGY 32 AND 64 MBIT

Intel 

INTEL® StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

E

are valid. Likewise, the device has a wake time

(tPHWL) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset

and the status register is cleared.

The Intel StrataFlash memory devices are

available in several package types. The 64-Mbit is

available in 56-lead SSOP (Shrink Small Outline

Package) and µBGA* package (micro Ball Grid

Array). The 32-Mbit is available in 56-lead TSOP

(Thin Small Outline Package) and 56-lead SSOP.

Figures 2, 3, and 4 show the pinouts.

VCCQ

32-Mbit: A0- A21

64-Mbit: A0 - A22

Input Buffer

Address

Latch

Address

Counter

DQ0 - DQ15

Y-Decoder

X-Decoder

Output Buffer

Input Buffer

Query

Identifier

Register

Status

Register

Data

Comparator

Y-Gating

Multiplexer

32-Mbit: Thirty-two

64-Mbit: Sixty-four

128-Kbyte Blocks

Command

User

Interface

I/O Logic

CE

Logic

VCC

BYTE#

CE0

CE1

CE2

WE#

OE#

RP#

Write State

Machine

Program/Erase

Voltage Switch

STS

VPEN

VCC

GND

0606_01

Figure 1. Intel® StrataFlash™ Memory Block Diagram

6

PRELIMINARY

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