MTD800 データシートの表示（PDF） - Myson Century Inc

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MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

4.2 Command and Status Registers

The MTD800 Command and Status Registers (CSRs) are mapped into the host I/O or the host memory

address space through the base addresses defined in the PCI configuration registers. The CSRs are quad-

byte aligned, 32-bit long, and must be accessed using longword instructions with quadbyte-aligned addresses

only. Following is the word layout table for CSRs.

Table 4.11 MTD800 Internal Command and Status Registers Layout

Offset

Address

00

PAR3

PAR2

PAR1

PAR0

04

-

-

PAR5

PAR4

08

MAR3

MAR2

MAR1

MAR0

0C

MAR7

MAR6

MAR5

MAR4

10

FAR3

FAR2

FAR1

FAR0

14

-

-

FAR5

FAR4

18

TCR

RCR

1C

BCR

Operation

RW

RW

RW

RW

RW

RW

RW

RW

20

Transmit poll demand

WO

24

Receive poll demand

WO

28

Receive current word pointer

RO

2C

Transmit list base address

WO

30

Receive list base address

WO

34

Interrupt Status Register

RW

38

Interrupt Mask Register

RW

3C

Flow Control High Threshold Flow Control Low Threshold

RW

40

BROM_CR SROM_CR

MII management

RW

44

Tally Counter CRC

Tally Counter MPA

RO

48

Tally Counter TSR

RO

4C

Filter A Byte Mask

WO

50

Filter A offset Filter A Cmd

Filter A CRC-16

RW

54

Filter B Byte Mask

WO

58

Filter B offset Filter B Cmd

Filter B CRC-16

RW

5C

Wake-up Events CSR

RW

78

TX FIFO Dump Register

RO

7C

RX FIFO Dump Register

RO

80

Function Event Register

RW

84

Function Event Mask Register

RW

88

Function Present State Register

RO

8C

Function Force Event Register

WO

24/42

MTD800 Revision 0.0 07/20/1999

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