MTD800 データシートの表示（PDF） - Myson Century Inc

部品番号

コンポーネント説明

メーカー

MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

Name

Field Descr iption

Power Management Block ( offset 88H)

PME Suppor t

31

If this bit is set, the chip asserts PME in D3cold power state. Other-

D3cold

wise, the chip does not asset PME in this power state. The value is

loaded from EEPROM.

PME Suppor t

30

This field is har dwir ed to 1. The chip dose support D3hot power

D3hot

state.

PME Suppor t D2 29

This field is har dwir ed to 0. The chip dose not support D2 power

state.

PME Suppor t D1 28

If this bit is set, the chip asserts PME in D1 power state. Otherwise,

the chip does not asset PME in this power state. The value is loaded

from EEPROM.

PME Suppor t D0 27

This field is har dwir ed to 0. The chip dose not support PME dur-

ing power state D0.

D2 Suppor t

26

This field is har dwir ed to 0. The chip dose not support D2 power

state.

D1 Suppor t

25

This field is har dwir ed to 1. The chip supports D1 power state.

Reser ved

24 - 22 This field is har dwir ed to 0.

Device Specific

21

Initialization

This field is har dwir ed to 0, indicating that the chip does not

require a special initialization code sequence in order to be config-

ured correctly.

Reser ved

20

This field is har dwir ed to 0.

Power Manage-

19

ment Event Clock

This field is har dwir ed to 0, indicating that the chip does not rely

on the presence of the CardBus clock in order to generate a PME.

Power Manage-

18 - 16 This field is har dwired to “001”, indicating that the chip complies

ment PCI Ver sion

with revision 1 of the PCI Power Management Specification.

Next Item Pointer 15 - 8

This field is har dwir ed to 8’h00, indicating that this is the last

item of the Capability linked list.

Capabilities ID

7-0

This field is har dwir ed to 8’h01, indicating that this is the power-

management register block.

Power -Management Contr ol and Status Register ( offset 8CH)

PME_status

Bit 15

When set, indicates that the chip has detected a power-management

event. This bit is cleared on power-up reset or by write 1. It is not

modified by software reset.

PME_Enable

Bit 8

When set, indicates that the chip can assert wake-up event pin. This

bit is cleared on power-up reset. The value of this field is loaded

from EEPROM.

Power State

Bit 1 - 0 The definition of the field values are 0 -D0, 1 - D1, 2 - Not defined

and 3 - D3cold. The field gets a value of 0 after power-up.

23/42

MTD800 Revision 0.0 07/20/1999

Share Link: