ITG3200 データシートの表示（PDF） - Unspecified
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ITG3200 Datasheet PDF : 39 Pages
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ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
To write the internal ITG-3200 device registers, the master transmits the start condition (S), followed by the I2C address
and the write bit (0). At the 9th clock cycle (when the clock is high), the ITG-3200 device acknowledges the transfer.
Then the master puts the register address (RA) on the bus. After the ITG-3200 acknowledges the reception of the
register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer
may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue
outputting data rather than transmitting a stop signal. In this case, the ITG-3200 device automatically increments the
register address and loads the data to the appropriate register. The following figures show single and two-byte write
sequences.
Single-Byte Write Sequence
Master S AD+W
RA
DATA
P
Slave
ACK
ACK
ACK
Burst Write Sequence
Master S AD+W
RA
DATA
DATA
P
Slave
ACK
ACK
ACK
ACK
To read the internal ITG-3200 device registers, the master first transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when clock is high), the ITG acknowledges the transfer. The master
then writes the register address that is going to be read. Upon receiving the ACK signal from the ITG-3200, the master
transmits a start signal followed by the slave address and read bit. As a result, the ITG-3200 sends an ACK signal and
the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK
condition is defined such that the SDA line remains high at the 9th clock cycle. To read multiple bytes of data, the
master can output an acknowledge signal (ACK) instead of a not acknowledge (NACK) signal. In this case, the ITG-
3200 automatically increments the register address and outputs data from the appropriate register. The following
figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master S AD+W
RA
S AD+R
NACK P
Slave
ACK
ACK
ACK DATA
Burst Read Sequence
Master S AD+W
RA
S AD+R
ACK
NACK P
Slave
ACK
ACK
ACK DATA
DATA
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