MWCT1001AVLH データシートの表示（PDF） - Freescale Semiconductor

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MWCT1001AVLH

Automotive Wireless Transmitter Controller

Freescale Semiconductor 

TBREAK

Minimum break character length

13

-

Mater node

bit periods

11

-

Slave node

bit periods

CAN Timing

Symbol

BRCAN

TWAKEUP

TWAKEUP

Characteristic

Baud rate

CAN Wakeup dominant pulse filtered

CAN Wakeup dominant pulse pass

Min.

-

-

5

Max.

1

1.5/2

-

Unit

Mbit/s

µs

µs

Notes

71

IIC Timing

Symbol

Characteristic

Min.

Min.

Max.

Max.

Unit Notes

Min.

Max.

fSCL

tHD_STA

tSCL_LOW

tSCL_HIGH

tSU_STA

tHD_DAT

tSU_DAT

tr

tf

SCL clock frequency

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START

condition

Data hold time for IIC bus devices

Data set-up time

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

0

100

0

400 kHz

4

-

0.6

-

µs

4.7

-

4

-

1.3

-

µs

0.6

-

µs

4.7

-

0.6

-

µs

072

3.4573

074

0.972

µs

25075

-

10076

-

ns

73

-

1000 20 + 0.1Cb 300

ns

77

-

300 20 + 0.1Cb 300

ns

76

tSU_STOP

Set-up time for STOP condition

4

-

0.6

-

µs

tBUS_Free

Bus free time between STOP and START

condition

4.7

-

1.3

-

µs

tSP

Pulse width of spikes that must be

suppressed by the input filter

N/A

N/A

0

50

ns

1. CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured

from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode.

2. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO.

3. Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO.

4. Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO.

5. WCT1001A supports maximum 100 MHz CPU clock and 50 MHz peripheral bus clock, maximum 100 MHz CPU and peripheral bus

clock for WCT1003A. In total, WCT1003A has higher power consumption than WCT1001A in the same operating mode. For the

current consumption data, the former is for WCT1001A, and the latter for WCT1003A.

6. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be

greater than 21 ns.

7. TOSC means oscillator clock cycle; TSYSCLK means system clock cycle.

8. During 3.3 V VDD power supply ramp down.

9. During 3.3 V VDD power supply ramp up (gated by LVI_2p7).

10. The maximum TCK operation frequency is fSYSCLK/8 for WCT1001A, fSYSCLK/16 for WCT1003A.

11. Value is after trim.

Automotive Wireless Transmitter Controller, Rev. 1.0, 08/2014

Freescale Semiconductor

19

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