XRT83VSH38 データシートの表示（PDF） - Exar Corporation
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XRT83VSH38 Datasheet PDF : 76 Pages
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REV. 1.0.7
XRT83VSH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
SIGNAL NAME
BGA
LEAD #
MCLKE1
J1
CLKSEL0
A8
CLKSEL1
B8
CLKSEL2
C8
TYPE
DESCRIPTION
I E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of
40% to 60% can be provided at this pin. In systems that have only one master clock
source available (E1 or T1), that clock should be connected to both MCLKE1 and
MCLKT1 inputs for proper operation.
NOTE: All channels of the XRT83VSH38 must be operated at the same clock rate,
either T1, E1 or J1. This pin is internally pulled “Low” with a 50kΩ resistor.
I Clock Select inputs for Master Clock Synthesizer
Hardware Mode Only
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
used to generate a master clock from an external accurate clock source according to
the table below. MCLKRATE is automatically generated from the state of the
EQC[4:0] pins.
MCLKE1 MCLKT1
kHz
kHz
CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE
2048
2048
0
0
0
0
2048
2048
0
0
0
1
2048
1544
0
0
0
0
1544
1544
0
0
1
1
1544
1544
0
0
1
0
2048
1544
0
0
1
1
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
CLKOUT/
kHz
2048
1544
2048
1544
2048
1544
12
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