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WM8731SEDS/RV データシートの表示(PDF) - Cirrus Logic

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WM8731SEDS/RV Datasheet PDF : 65 Pages
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WM8731 / WM8731L
Production Data
ELECTRICAL CHARACTERISTICS – WM8731
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
Input HIGH level
VIH
Output LOW
VOL
0.7 x DBVDD
0.3 x DBVDD
V
V
0.10 x
V
DBVDD
Output HIGH
VOH
0.9 x DBVDD
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Vth
Hysteresis
VIH
DCVDD Threshold Off -> On
VOL
Analogue Reference Levels
0.9
V
0.3
V
0.6
V
Reference voltage (VMID)
Potential divider resistance
Line Input to ADC
VVMID
RVMID
AVDD/2
V
50k
Input Signal Level (0dB)
VINLINE
1.0
AVDD/3.3
Vrms
Signal to Noise Ratio
SNR
A-weighted, 0dB gain
85
90
dB
(Note 1,3)
@ fs = 48kHz
A-weighted, 0dB gain
90
@ fs = 96kHz
A-weighted, 0dB gain
88
@ fs = 48kHz,
AVDD = 2.7V
Dynamic Range (Note 3)
DR
A-weighted, -60dB full
85
90
dB
scale input
Total Harmonic Distortion
THD
-1dB input, 0dB gain
-84
-74
dB
0.006
0.02
%
Power Supply Rejection Ratio
PSRR
1kHz, 100mVpp
50
dB
20Hz to 20kHz,
45
100mVpp
ADC channel separation
1kHz input
90
dB
Programmable Gain
1kHz input
-34.5
0
+12
dB
Rsource < 50
Programmable Gain Step Size
Guaranteed Monotonic
1.5
dB
Mute attenuation
0dB, 1kHz input
80
dB
Input Resistance
RINLINE
0dB gain
20k
30k
12dB gain
10k
15k
Input Capacitance
CINLINE
10
pF
w
PD, Rev 4.9, October 2012
7

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